Utilizing variable-length inputs in an inter-sequence permutation turbo code system

ABSTRACT

The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means. Further, the ISP encoder comprises a third outputting means coupled to the bit-adding means to output a third code bit output or directly coupled to the receiving means. Alternatively, the ISP encoder comprises a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.

The present application is a continuation-in-part application of U.S. application Ser. No. 11/176,829, which is entitled “AN INTER-SEQUENCE PERMUTATION TURBO CODE SYSTEM AND OPERATION METHODS THEREOF,” and U.S. application Ser. No. 11/414,433, which is entitled “NETWORK FOR PERMUTATION OR DE-PERMUTATION UTILIZED BY CHANNEL CODING ALGORITHM.”

BACKGROUND OF THE INVENTION

(A) Field of the Invention

The present application relates to a method of utilizing variable-length inputs in an inter-sequence permutation turbo code system.

(B) Description of Related Art

In U.S. application Ser. No. 11/176,829 and U.S. application Ser. No. 11/414,433, an improved turbo code system is disclosed. However, persons skilled in the art may have noted that the ability of this system is limited. When all the sequence permuters (the first sequence permuter or the second sequence permutor in U.S. application Ser. No. 11/176,829) permute sequences with the same length, the system can only deal with inputted sequence (at encoder side) having the length of information bit sequence dividable to the length processed by the permuter without any remainder. However, this limit is undesired since practically information bit sequence can be of any length. The present invention is thus a solution to this problem and a teaching in utilizing an inputted sequence with variable-length in the inter-sequence permutation (ISP) turbo code system. The method can be further applied for the turbo code applying the almost regular permutation (ARP) interleaver, which is another kind of the inter-sequence permutation interleaver.

SUMMARY OF THE INVENTION

The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprising a receiving means for receiving an information bit sequence input; a first outputting means through which a first code bit sequence output is outputted; a second outputting means through which a second code bit sequence output is outputted; a bit-adding means coupled to the receiving means, the bit-adding (symbol-adding) means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver. The inter-sequence permutation interleaver is coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutation interleaver and the second outputting means.

Further, the ISP encoder comprises a third outputting means through which a third code bit sequence output is outputted, wherein the third outputting means is coupled to the bit-adding means or directly coupled to the receiving means.

Alternatively, the ISP encoder comprises a fourth outputting means through which a fourth code bit sequence output is outputted, wherein the fourth outputting means is coupled to the inter-sequence permutation interleaver.

The present invention also relates to an inter-sequence permutation encoder. The ISP encoder comprises a receiving means for receiving an information bit sequence input; a first outputting means for outputting a first code bit sequence output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, wherein the bit-adding means processes the received information bit sequence input prior to any subsequent processing of the received information bit sequence input in the inter-sequence permutation encoder; a first convolutional code encoder coupled between the receiving means and the first outputting means; and a second convolutional code encoder coupled to the second outputting means; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. Further, the ISP encoder comprises a third outputting means coupled to the receiving means to output a third code bit sequence output.

Alternatively, the ISP encoder comprises a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is described below by way of examples with reference to the accompanying drawings which will make it easier for readers to understand the purpose, technical contents, characteristics and achievement of the present invention, wherein FIG. 1 shows an example illustrating “shortening” and “puncturing” utilized in the ISP turbo code encoder;

FIG. 2 shows a first embodiment of the ISP encoder of the present invention;

FIG. 3 shows a second embodiment of the ISP encoder of the present invention;

FIG. 4 shows a third embodiment of the ISP encoder of the present invention;

FIG. 5 shows a fourth embodiment of the ISP encoder of the present invention; and

FIG. 6 shows a fifth embodiment of the ISP encoder of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The detailed description of a preferred embodiment is intended to illustrate the present invention, and is not intended to limit forms to embody the present invention.

Techniques that the invention adopts are conventional “shortening” and “puncturing.” Please first refer to FIG. 1. We assume that an inputted, first sequence 101 comprises 13 bits and all the sequence permuters process 4 bits. According to U.S. application Ser. No. 11/176,829 and U.S. application Ser. No. 11/414,433, such a sequence is not a valid sequence input to the ISP turbo code encoder. However, by adding three “0” bits in the sequence 101, it becomes a second sequence 102, which can be divided by 4 without leaving any remainder. Although we add “0” in this case, adding other kinds of symbol is also possible, e.g. “1”. Although we add three “0” at the end, exchanging prior information bits with at least one “0” is also possible. Please also note that meanings of “bit” and “symbol” can be interchanged in the present specification. An individual who fully understands the bit-adding operation could realize that adding bits makes the extended length of bit sequence valid for inputting to the inter-sequence permutation interleaver.

The sequence 102 can be permuted and encoded by the encoder performing inter-sequence permutation and convolutional code encoding (both have been discussed in U.S. application Ser. No. 11/176,829), the second sequence 102 becomes a third sequence 103 and a fourth sequence 104. In the third sequence 103 underlined digits in a sequence represent “added” bits. In the fourth sequence 104 underlined digits in a sequence represent “punctured” bits. After the process of inter-sequence permutation and/or convolutional code encoding, the added bits or the punctured bits are taken away, the resulting sequences are a fifth sequence 103′ and a sixth sequence 104′ respectively.

Adding the added bits before encoding and removing the added bits after encoding is called “shortening.” Removing the punctured bits is called “puncturing.” The shortening makes that the ISP turbo code system can encode a variable-length information bit sequence encodable when the length of information bit sequence is smaller than the designed length processed by the ISP turbo coding system. The puncturing makes that the length of code bit length matches the desired code bit length and the resultant code rate matches the desired code rate. One would easily note that essentially operations for removing the added bits and removing the punctured bits are very similar; therefore, we will uniformly call them “deleting” in the specification of the present application. However readers should keep in mind that in practice one would use different terms to refer to the deleting operation.

After the added bits are taken away, in order to increase bandwidth efficiency, the outputted “code bit sequences” can be further punctured, individually or jointly. This technique of “further puncturing” has been widely known, and we will just skip detailed description here.

The techniques described in previous 2 paragraphs and FIG. 1 can be embodied in U.S. application Ser. No. 11/176,829 and U.S. application Ser. No. 11/414,433 in various ways shown as follows. In FIGS. 2-4, receiving means and outputting means indicate physical portions for receiving and outputting sequences, respectively. They can be devices, circuit blocks, terminals, contacts, or simply wire junctions.

FIG. 2 is a first embodiment of the present invention, which evolves from FIG. 2 of U.S. application Ser. No. 11/176,829 by choosing outputs 106, 107 and 108 in FIG. 2 of U.S. application Ser. No. 11/176,829. In U.S. application Ser. No. 11/176,829, only three outputs (106, 107, 108, or 107, 108, 109) are required.

In FIG. 2, a bit-adding means 203 adds bits to an information bit sequence input received from a receiving means 202. After processed by the ISP encoder, every code bit sequence output at the first outputting means 207, second outputting means 208, and third outputting means 209 is subjected to a deleting operation in order to eliminate the “added” or “punctured” bits. As mentioned before, at least an additional puncturing operation can be further performed on the code bit sequence output in order to increase the bandwidth efficiency.

In FIG. 3, similarly every code bit sequence output at the first outputting means 207, second outputting means 208, and fourth outputting means 301 is subjected to a deleting operation in order to eliminate the “added” bits. As mentioned before, at least an additional puncturing operation can be further performed on the code bit sequence output in order to increase the bandwidth efficiency.

In FIG. 4, the third outputting means is directly coupled to the receiving means 202, thus eliminating the need to perform the deleting operation at the third outputting means 209. Similarly, every code bit output at the first outputting means 207 and second outputting means 208 is still subjected to a deleting operation in order to eliminate the “punctured” bits. As mentioned before, at least an additional puncturing operation can be further performed on the code bit sequence output in order to increase the bandwidth efficiency.

Encoders shown in FIG. 5 and FIG. 6 are similar to those in FIG. 4 and FIG. 3, respectively. A difference lies in that the first convolutional code encoder 205 directly receives sequences from the receiving means 202, since not all methods of convolutional code encoding requires “shortening” or “puncturing” beforehand. As mentioned before, at least an additional puncturing operation can be further performed on the code bit sequence output in order to increase the bandwidth efficiency.

In FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG. 6, the first and second convolutional code encoders can adopt as least one of the following methods: tail-biting convolutional encoding, tail-padding convolutional code encoding. The convolutional code encoders can be replaced by other encoding methods such as Reed-Muller code, BCH code . . . etc. Multiple sequences after and before inter-sequence permutation interleaver can be separately encoded.

Naturally, an individual who fully understand the present invention could realize that in fact, only sequences passing through the inter-sequence permutation interleaver requires “shortening” or “puncturing” operations. Therefore, the deleting operations do not require to be only performed at the outputting means. They can be performed right following the inter-sequence permutation interleaver, or prior to a convolutional code encoder if sequences passing through that convolutional code encoder do not require “shortening” or “puncturing.”

The almost regular permutation is also a kind of inter-sequence permutation interleaver and the “shortening” or “puncturing” can be applied for the turbo code applying the almost regular permutation as interleaver to encode a bit sequence with variable length. 

1. An inter-sequence permutation encoder, at least comprising: a receiving means for receiving an information bit sequence input; a first outputting means for outputting a first code bit sequence output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, wherein the bit-adding means processing the received information bit sequence input prior to any subsequent processing of the received information bit sequence input in the inter-sequence permutation encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; and a second convolutional code encoder coupled to the second outputting means; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder.
 2. The inter-sequence permutation encoder as claimed in claim 1, further comprising a third outputting means coupled to the bit-adding means to output a third code bit sequence output.
 3. The inter-sequence permutation encoder as claimed in claim 1, further comprising a third outputting means coupled to the receiving means to output a third code bit sequence output.
 4. The inter-sequence permutation encoder as claimed in claim 1, further comprising a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.
 5. The inter-sequence permutation encoder as claimed in claim 1, wherein the first and second convolutional code encoders perform as least one of the following methods: tail-biting convolutional encoding, tail-padding convolutional code encoding.
 6. The inter-sequence permutation encoder as claimed in claim 1, wherein methods adopted by the convolutional code encoders are replaced by at least one of the following methods: Reed-Muller code and BCH code.
 7. The inter-sequence permutation encoder as claimed in claim 1, wherein sequences processed after and before the inter-sequence permutation interleaver are separately encoded.
 8. The inter-sequence permutation encoder as claimed in claim 1, wherein the first and second outputting means perform deleting operations in order to eliminate bits added by the bit-adding means.
 9. The inter-sequence permutation encoder as claimed in claim 2, wherein the third outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means.
 10. The inter-sequence permutation encoder as claimed in claim 4, wherein the fourth outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means.
 11. The inter-sequence permutation encoder as claimed in claim 1, wherein the first and second code bit sequence outputs undergo at least an additional puncturing operation.
 12. The inter-sequence permutation encoder as claimed in claim 2, wherein the third code bit sequence output undergoes at least an additional deleting operation.
 13. The inter-sequence permutation encoder as claimed in claim 3, wherein the third code bit sequence output undergoes at least an additional deleting operation.
 14. The inter-sequence permutation encoder as claimed in claim 4, wherein the fourth code bit sequence output undergoes at least an additional deleting operation.
 15. The inter-sequence permutation encoder as claimed in claim 6, wherein the first or second code bit sequence output undergoes at least an additional puncturing operation.
 16. The inter-sequence permutation encoder as claimed in claim 9, wherein the third code bit sequence output undergoes at least an additional puncturing operation.
 17. The inter-sequence permutation encoder as claimed in claim 10, wherein the fourth code bit sequence output undergoes at least an additional puncturing operation.
 18. An inter-sequence permutation encoder, at least comprising: a receiving means for receiving an information bit sequence input; a first outputting means for outputting a first code bit sequence output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, wherein the bit-adding means processes the received information bit sequence input prior to any subsequent processing of the received information bit sequence input in the inter-sequence permutation encoder; a first convolutional code encoder coupled between the receiving means and the first outputting means; a second convolutional code encoder coupled to the second outputting means; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder.
 19. The inter-sequence permutation encoder as claimed in claim 18, further comprising a third outputting means coupled to the receiving means to output a third code bit sequence output.
 20. The inter-sequence permutation encoder as claimed in claim 18, further comprising a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.
 21. The inter-sequence permutation encoder as claimed in claim 18, wherein the first and second convolutional code encoders perform as least one of the following methods: tail-biting convolutional encoding, tail-padding convolutional code encoding.
 22. The inter-sequence permutation encoder as claimed in claim 18, wherein methods adoped by the convolutional code encoders are replaced by at least one of the following methods: Reed-Muller code and BCH code.
 23. The inter-sequence permutation encoder as claimed in claim 18, wherein sequences processed after and before the inter-sequence permutation interleaver are separately encoded.
 24. The inter-sequence permutation encoder as claimed in claim 18, wherein the second outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means.
 25. The inter-sequence permutation encoder as claimed in claim 20, wherein the fourth outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means.
 26. The inter-sequence permutation encoder as claimed in claim 24, wherein the first or second code bit sequence output undergoes at least an additional puncturing operation.
 27. The inter-sequence permutation encoder as claimed in claim 19, wherein the third code bit sequence output undergoes at least an additional puncturing operation.
 28. The inter-sequence permutation encoder as claimed in claim 25, wherein the fourth code bit sequence output undergoes at least an additional puncturing operation. 